A LOW POWER 72.8 GHz STATIC FREQUENCY DIVIDER IMPLEMENTED IN AlInAsAnGaAs HBT IC TECHNOLOGY

We report a 72.8 GHz fully static frequency divider in AIInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than OdBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8GHz. Power dissipation per flip-flop is 55mW with a 3.1V power supply. To our knowledge this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is also the lowest power-delay product for a circuit operating above SOGHz in any technology. A low power divider on the same substrate operates at 36 GHz with 6.9mW of dissipated power per flip-flop with a 3.1V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power delay product for a static divider operating above 3OGHz in any technology.